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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14067B MC14097B Analog Multiplexers/Demultiplexers
The MC14067 and MC14097 multiplexers/demultiplexers are digitally controlled analog switches featuring low ON resistance and very low leakage current. These devices can be used in either digital or analog applications. The MC14067 is a 16-channel multiplexer/demultiplexer with an inhibit and four binary control inputs A, B, C, and D. These control inputs select 1-of-16 channels by turning ON the appropriate analog switch (see MC14067 truth table.) The MC14097 is a differential 8-channel multiplexer/demultiplexer with an inhibit and three binary control inputs A, B, and C. These control inputs select 1 of 8 pairs of channels by turning ON the appropriate analog switches (see MC14097 truth table). * * * * * * * Low OFF Leakage Current Matched Channel Resistance Low Quiescent Power Consumption Low Crosstalk Between Channels Wide Operating Voltage Range: 3 to 18 V Low Noise Pin for Pin Replacement for CD4067B and CD4097B
L SUFFIX CERAMIC CASE 623
P SUFFIX PLASTIC CASE 709
DW SUFFIX SOIC CASE 751E
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
MC14067B 16-Channel Analog Multiplexer/Demultiplexer
15 10 11 14 13 9 8 7 6 5 4 3 2 23 22 21 20 19 18 17 16 INHIBIT A B C D X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
MC14097B Dual 8-Channel Analog Multiplexer/Demultiplexer
13 10 11 14 9 8 7 6 5 4 3 2 23 22 21 20 19 18 16 15 INHIBIT A B C X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
CONTROLS
CONTROLS
X
1
X
COMMON 1 OUT/IN SWITCHES IN/OUT
SWITCHES IN/OUT
COMMONS OUT/IN
Y
17
VDD = PIN 24 VSS = PIN 12
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14067B MC14097B 1
IIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I IIIIIII I I I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage Value Unit V V - 0.5 to + 18.0 Vin, Vout Iin Input or Output Voltage (DC or Transient) Input Current (DC or Transient), per Control Pin Switch Through Current - 0.5 to VDD + 0.5 10 25 500 mA mA Isw PD Power Dissipation, per Package Storage Temperature mW Tstg TL - 65 to + 150 260
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
Lead Temperature (8-Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
MC14067 TRUTH TABLE
Control Inputs A X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inh 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Selected Channel None X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
MC14097 TRUTH TABLE
Control Inputs A X 0 1 0 1 0 1 0 1 B X 0 0 1 1 0 0 1 1 C X 0 0 0 0 1 1 1 1 Inh 1 0 0 0 0 0 0 0 0 Selected Channels None X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X = Don't Care
MC14067 FUNCTIONAL DIAGRAM
INHIBIT A B C D X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
MC14097 FUNCTIONAL DIAGRAM
INHIBIT A B C X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
CONTROL INPUTS
1-OF-16 DECODER
CONTROL INPUTS
1-OF-8 DECODER
X IN/OUT X OUT/IN Y IN/OUT
X OUT/IN
X IN/OUT
Y OUT/IN
MC14067B MC14097B 2
MOTOROLA CMOS LOGIC DATA
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SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y (Voltages Referenced to VSS) CONTROL INPUTS -- INHIBIT, A, B, C, D (Voltages Referenced to VSS) SUPPLY REQUIREMENTS (Voltages Referenced to VSS)
Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance. ** For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)
ELECTRICAL CHARACTERISTICS
Capacitance, Feedthrough (Channel Off)
Capacitance, Common O/I
Capacitance, Switch I/O
Off-Channel Leakage Current (Figure 2)
ON Resistance Between Any Two Channels in the Same Package
ON Resistance
Output Offset Voltage
Recommended Static or Dynamic Voltage Across the Switch'* (Figure 1)
Recommended Peak-to- Peak Voltage Into or Out of the Switch
Input Capacitance
Input Leakage Current
High-Level Input Voltage
Low-Level Input Voltage
Total Supply Current (Dynamic Plus Quiescent, Per Package
Quiescent Current Per Package
Power Supply Voltage Range
MOTOROLA CMOS LOGIC DATA
Characteristic Vswitch Symbol ID(AV) Ron VOO VDD CI/O CO/I CI/O VI/O Ron IDD VIH Cin VIL Ioff Iin VDD 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 -- -- -- -- -- -- -- -- -- Control Inputs: Vin = VSS or VDD, Switch I/O: VSS VI/O VDD, and Vswitch mV** Pins Not Adjacent Pins Adjacent Inhibit = VDD (MC14067B) (MC14097B) Inhibit = VDD Vin = VIL or VIH (Control) Channel to Channel or Any One Channel Vswitch 500 mV**, Vin = VIL or VIH (Control), and Vin 0 to VDD (Switch) Vin = 0 V, No Load Channel On Channel On or Off Vin = 0 or VDD Ron = per spec, Ioff = per spec Ron = per spec, Ioff = per spec TA = 25_C only (The channel component, (Vin - Vout)/Ron, is not included.)
v
Test Conditions
v
v v500
Min
3.5 7.0 11
3.0
--
-- --
--
--
-- -- --
-- -- --
--
--
--
-- -- --
-- -- --
0
0
- 55C
Typical
100
VDD
Max
0.1
800 400 220
600
1.5 3.0 4.0
5.0 10 20
70 50 45
18
--
-- --
--
--
--
-- -- --
Min
3.5 7.0 11
3.0
--
-- --
--
--
-- -- --
-- -- --
--
--
--
-- -- --
-- -- --
0
0
(0.07 A/kHz) f + IDD (0.20 A/kHz) f + IDD (0.36 A/kHz) f + IDD
0.00001
0.05
Typ #
0.005 0.010 0.015
25_C
0.47
2.75 5.50 8.25
2.25 4.50 6.75
100 60
250 120 80
5.0
10
25 10 10
10
--
--
--
100
1050 500 280
VDD
Max
0.1
600
7.5
1.5 3.0 4.0
5.0 10 20
70 50 45
18
--
-- --
--
--
-- -- --
MC14067B MC14097B 3
Min 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 125_C 1000 1300 550 320 VDD Max 135 95 65 300 150 300 600 1.0 1.5 3.0 4.0 18 -- -- -- -- -- -- -- -- -- Vp-p Unit mV V A A A nA pF pF pF pF V V V
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Crosstalk, Control Inputs-to-Common O/I (R1 = 1 k, RL = 10 k, Control tr = tf = 20 ns, Inhibit = VSS)
Channel Separation [RL = 1 k, Vin = 1/2 (VDD-VSS) p-p (sine-wave)]
Off Channel Feedthrough Attenuation [RL = 1 k, Vin = 1/2 (VDD-VSS) p-p(sine-wave)] fin = 20 MHz - MC14067B fin = 12 MHz - MC14097B
ON Channel Bandwidth [RL = 1 k, Vin = 1/2 (VDD - VSS) p-p(sine-wave)] 20 Log10 (Vout/Vin) = - 3 dB
Second Harmonic Distortion (RL = 10 k, f = 1 kHz, Vin = 5 Vp-p)
Propagation Delay Times Channel Input-to-Channel Output (RL = 200 k) MC14067B
MC14067B MC14097B 4
Any Pair of Address Inputs to Output MC14067B Channel Turn-Off Time (RL = 300 k) MC14067B/097B Control Input-to-Channel Output Channel Turn-On Time (RL = 10 k) MC14067B/097B MC14097B MC14097B Characteristic fin = 20 MHz MC14067B MC14097B tPLH, tPHL tPZH, tPZL (Figure 10) tPLH, tPHL tPHZ, tPLZ (Figure 4) (Figure 7) (Figure 6) (Figure 5) (Figure 4) (Figure 3) (Figure 5) Symbol BW -- -- -- -- 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 10 10 10 10 10 10
VDD - VSS Vdc
MOTOROLA CMOS LOGIC DATA
Typ # - 40 - 40 250 100 75 280 115 85 250 120 75 240 115 75 0.3 30 15 25 25 10 7 35 15 12 Max 625 250 190 700 290 215 625 300 190 600 290 190 65 25 18 90 40 30 -- -- -- -- -- -- MHz Unit mV dB dB ns ns ns ns ns ns %
ON SWITCH CONTROL SECTION OF IC LOAD V CONTROL SECTION OF IC
OFF CHANNEL UNDER TEST VDD A VSS OTHER CHANNEL(S)
VSS VDD
SOURCE
VSS VDD
Figure 1. V Across Switch
Figure 2. Off Channel Leakage
MC14067B PIN ASSIGNMENT
X X7 X6 X5 X4 X3 X2 X1 X0 A B VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD X8 X9 X10 X11 X12 X13 X14 X15 INHIBIT C D
MC14097B PIN ASSIGNMENT
X X7 X6 X5 X4 X3 X2 X1 X0 A B VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD Y0 Y1 Y2 Y3 Y4 Y5 Y Y6 Y7 C INHIBIT
MOTOROLA CMOS LOGIC DATA
MC14067B MC14097B 5
VC VDD A B C D INH Vin 20 ns Vin tPLH Vout 20 ns 90% 50% tPHL 50% VDD 10% VSS Vout VC RL PULSE GENERATOR
A B C D INH RL Vin VX
Vout CL = 50 pF
Vout CL = 50 pF 20 ns
VDD VSS VSS VDD 20 ns 90% 50% 10% 90% 50% tPZH, tPZL Vout 50% 10% Vin = VDD VX = VSS Vin = VSS VX = VDD
tPHZ, tPLZ
Figure 3. Propagation Delay Test Circuit and Waveforms Vin to Vout
Figure 4. Turn-On and Delay Turn-Off Test Circuit and Waveforms
A, B, and C inputs used to turn ON or OFF the switch under test. A B C D INH Vin RL
VDD A B C D INH ON
RL
OFF RL Vin
Vout CL = 50 pF
Vout CL = 50 pF
Figure 5. Bandwidth and Off-Channel Feedthrough Attenuation
Figure 6. Channel Separation (Adjacent Channels Used for Setup)
VC
A B C D INH R1 RL
Vout CL = 50 pF
Figure 7. Crosstalk, Control to Common O/I
MC14067B MC14097B 6
MOTOROLA CMOS LOGIC DATA
VA VB
A B C D INH VDD
VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k VDD 1 k RANGE
CL
Vout
VA
50%
X-Y PLOTTER
VB tPHL Vout
50% tPLH 50%
VSS
Figure 8. Channel Resistance (RON) Test Circuit
Figure 9. Propagation Delay, Any Pair of Address Inputs to Output
TYPICAL RESISTANCE CHARACTERISTICS
350 R ON , "ON" RESISTANCE (OHMS) R ON , "ON" RESISTANCE (OHMS) 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 350 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 TA = 125C 25C - 55C
TA = 125C 25C - 55C
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 10. VDD = 7.5 V, VSS = - 7.5 V
Figure 11. VDD = 5.0 V, VSS = - 5.0 V
700 R ON , "ON" RESISTANCE (OHMS) RON , "ON" RESISTANCE (OHMS) 600 500 400 300 TA = 125C 200 25C 100 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 - 55C 4.0 6.0 8.0 10
350 300 250 200 150 5.0 V 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 7.5 V TA = 25C
VDD = 2.5 V
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 2.5 V, VSS = - 2.5 V MOTOROLA CMOS LOGIC DATA
Figure 13. Comparison at 25C, VDD = - VSS MC14067B MC14097B 7
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Multiplexer/Demultiplexer. The 0-to-5 volt Digital Control signal is used to directly control a 5 Vp-p analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example. VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and VSS. The analog voltage must swing neither higher than V DD nor lower than V SS. The example shows a 5 V p-p signal which allows no margin at either peak. If voltage transients above VDD and/or below VSS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VSS is 18.0 volts. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and VSS.
+5 V VDD VSS + 5.0 V 5 Vp-p ANALOG SIGNAL +5 V SWITCH I/O
COMMON O/I
5 Vp-p ANALOG SIGNAL
+ 2.5 V
EXTERNAL CMOS DIGITAL CIRCUITRY
0-TO-5 V DIGITAL CONTROL SIGNALS
MC14067B MC14097B
GND
Figure A. Application Example
VDD DX SWITCH I/O DX VSS COMMON O/I
VDD DX
DX VSS
Figure B. External Germanium or Schottky Clipping Diodes
MC14067B MC14097B 8
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 623-05 ISSUE M
24 13 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). DIM A B C D F G J K L M N MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050
B
1 12
A
SEATING PLANE
F
C
L G D N K M J
P SUFFIX PLASTIC DIP PACKAGE CASE 709-02 ISSUE C
24 13 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040
B
1 12
A N K H G F D
SEATING PLANE
C
L
M
J
MOTOROLA CMOS LOGIC DATA
MC14067B MC14097B 9
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC14067B MC14097B 10
*MC14067B/D*
MOTOROLA CMOS LOGIC DATA MC14067B/D

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